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STM32F401CDU6 bảng dữ liệu(PDF) 106 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Clock, reset and supply management
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STM32F401CDU6 bảng dữ liệu(HTML) 106 Page - STMicroelectronics

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Electrical characteristics
STM32F401xD STM32F401xE
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Figure 39. USB OTG FS timings: definition of data signal rise and fall time
6.3.20
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 66 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 14.
Table 65. USB OTG FS electrical characteristics(1)
1. Guaranteed by design, not tested in production.
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF
420
ns
tf
Fall time(2)
CL = 50 pF
4
20
ns
trfm
Rise/ fall time matching
tr/tf
90
110
%
VCRS
Output signal crossover voltage
1.3
2.0
V
ai14137
tf
Differen tial
Data L ines
VSS
VCRS
tr
Crossover
points
Table 66. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
VDDA − VREF+ < 1.2 V
1.7(1)
-3.6
V
VREF+
Positive reference voltage
1.7(1)
-VDDA
V
fADC
ADC clock frequency
VDDA = 1.7(1) to 2.4 V
0.6
15
18
MHz
VDDA = 2.4 to 3.6 V
0.6
30
36
MHz
fTRIG(2) External trigger frequency
fADC = 30 MHz,
12-bit resolution
-
-
1764
kHz
--
17
1/fADC
VAIN
Conversion voltage range(3)
0 (VSSA or VREF-
tied to ground)
-VREF+
V
RAIN(2)
External input impedance
See Equation 1 for
details
--
50
k
Ω
RADC(2)(4) Sampling switch resistance
-
-
6
k
Ω
CADC(2)
Internal sample and hold
capacitor
-4
7
pF



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