STM32F302XD datasheet(124/168 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F302xD STM32F302xE

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DocID026900 Rev 4

Note:

Refer to the I2S section in RM0365 Reference Manual for more details about the sampling

frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source

clock precision might slightly change the values DCK depends mainly on ODD bit value.

Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of

(I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition.

Table 75. I2S characteristics(1)

1. Data based on characterization results, not tested in production.

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

I2S Main clock output

256 x 8K

256xFs (2)

2. 256xFs maximum is 36 MHz (APB1 Maximum frequency)

MHz

fCK

I2S clock frequency

Master data: 32 bits

64xFs

MHz

Slave data: 32 bits

64xFs

DCK

I2S clock frequency duty

cycle

Slave receiver

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

Slave mode

tsu(SD_MR)

Data input setup time

Master receiver

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

2.5

tv(SD_ST)

Data output valid time

Slave transmitter

(after enable edge)

-50

tv(SD_MT)

Master transmitter

(after enable edge)

-22

th(SD_ST)

Data output hold time

Slave transmitter (after

enable edge)

th(SD_MT)

Master transmitter

(after enable edge)

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