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STM32F302XD bảng dữ liệu(PDF) 121 Page - STMicroelectronics |
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STM32F302XD bảng dữ liệu(HTML) 121 Page - STMicroelectronics |
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121 / 168 page ![]() DocID026900 Rev 4 121/168 STM32F302xD STM32F302xE Electrical characteristics 146 SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 74 for SPI or in Table 75 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 19. Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 73. I2C analog filter characteristics(1) 1. Guaranteed by design, not tested in production. Symbol Parameter Min Max Unit tAF Pulse width of spikes that are suppressed by the analog filter 50 260 ns Table 74. SPI characteristics(1) Symbol Parameter Conditions Min Typ. Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 2.7 V<VDD<3.6 V, SPI1/4 -- 24 MHz Master mode 2 V<VDD<3.6 V, SPI1/2/3/4 18 Slave mode 2 V<VDD<3.6 V, SPI1/4 24 Slave mode 2 V<VDD<3.6 V, SPI1/2/3/4 18 Slave mode transmitter/full duplex 2 V<VDD<3.6 V, SPI1/2/3/4 16.5(2) Slave mode transmitter/full duplex 2.7 V<VDD<3.6 V, SPI1/4 22.5(2)) - Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 tsu(MI) Data input setup time Master mode 3 - - tsu(SI) Slave mode 3 - - th(MI) Data input hold time Master mode 6.5 - - th(SI) Slave mode 4.5 - - ta(SO) Data output access time Slave mode 10 - 30 tdis(SO) Data output disable time Slave mode 8 - 7 |
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