STM32F078CB datasheet(23/120 Pages) STMICROELECTRONICS

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DocID026006 Rev 4

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STM32F078CB, STM32F078RB, STM32F078VB

Functional overview

TIM15 can be synchronized with TIM16 and TIM17.

TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and

independent DMA request generation.

Their counters can be frozen in debug mode.

3.14.3

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as generic

16-bit time bases.

3.14.4

Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with

user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it

operates independently from the main clock, it can operate in Stop mode. It can be used

either as a watchdog to reset the device when a problem occurs, or as a free running timer

for application timeout management. It is hardware or software configurable through the

option bytes. The counter can be frozen in debug mode.

3.14.5

System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free

running. It can be used as a watchdog to reset the device when a problem occurs. It is

clocked from the APB clock (PCLK). It has an early warning interrupt capability and the

counter can be frozen in debug mode.

3.14.6

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

•

a 24-bit down counter

•

autoreload capability

•

maskable system interrupt generation when the counter reaches 0

•

programmable clock source (HCLK or HCLK/8)

3.15

Real-time clock (RTC) and backup registers

The RTC and the five backup registers are supplied through a switch that takes power either

on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit

registers used to store 20 bytes of user application data when VDD power is not present.

They are not reset by a system or power reset.

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