STM32F048C6 datasheet(23/98 Pages) STMICROELECTRONICS

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STM32F048C6 STM32F048G6 STM32F048T6

Functional overview

from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address

match.

The I2C peripheral can be served by the DMA controller.

3.15

Universal synchronous/asynchronous receiver/transmitter

(USART)

The device embeds two universal synchronous/asynchronous receivers/transmitters

(USART1, USART2) which communicate at speeds of up to 6 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals,

multiprocessor communication mode, master synchronous communication and single-wire

half-duplex communication mode. USART1 supports also SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a

clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.

The USART interfaces can be served by the DMA controller.

Table 8. STM32F048x6 I2C implementation

I2C features(1)

1. X = supported.

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with extra output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

Table 9. STM32F048x6 USART implementation

USART modes/features(1)

USART1

USART2

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

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