STM8L151X6 datasheet(89/146 Pages) STMICROELECTRONICS

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DocID17943 Rev 10

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STM8L151x6/8 STM8L152x6/8

Electrical parameters

123

9.3.4

Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of

VDD /2. Floating DAC output.

6. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2

enabled with static inputs. Supply current of internal reference voltage excluded.

7. Including supply current of internal reference voltage.

Table 28. Current consumption under external reset

Symbol

Parameter

Conditions

Typ.

Unit

IDD(RST)

Supply current under

external reset (1)

PB1/PB3/PA5 pins are

externally tied to VDD

VDD = 1.8 V

µA

VDD = 3 V

VDD = 3.6 V

1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.

Table 29. HSE external clock characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

fHSE_ext(1)

1. Guaranteed by design.

External clock source

frequency

116

MHz

VHSEH

OSC_IN input pin high level

voltage

0.7 x VDD

VDD

VHSEL

OSC_IN input pin low level

voltage

VSS

0.3 x VDD

Cin(HSE)(1) OSC_IN input capacitance

2.6

ILEAK_HSE

OSC_IN input leakage

current

VSS < VIN < VDD

±1

µA

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