ST72561J4-Auto datasheet(238/324 Pages) STMICROELECTRONICS

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beCAN controller (beCAN)

ST72561-Auto

238/324

Doc ID 12370 Rev 8

17.8

17.8.1

Control and status registers

CAN master control register (CMCR)

Reset value: 0000 0010 (02h)

Bit 7 = Reserved, must be kept cleared.

Bit 6 = ABOM Automatic Bus-Off Management

Read/set/clear

This bit controls the behaviour of the CAN hardware on leaving the bus-off state.

0: the bus-off state is left on software request.

Refer to Error management, bus-off recovery.

1: the bus-off state is left automatically by hardware once 128 x 11 recessive bits have

been monitored.

For detailed information on the bus-off state please refer to Error management.

Bit 5 = AWUM Automatic Wake-Up Mode

Read/set/clear

This bit controls the behaviour of the CAN hardware on message reception during sleep

mode.

0: the sleep mode is left on software request by clearing the SLEEP bit of the CMCR

1: the sleep mode is left automatically by hardware on CAN message detection. The

SLEEP bit of the CMCR register and the SLAK bit of the CMSR register are cleared by

hardware.

Bit 4 = NART No Automatic Retransmission

Read/set/clear

0: the CAN hardware will automatically retransmit the message until it has been

successfully transmitted according to the CAN standard.

1: a message will be transmitted only once, independently of the transmission result

(successful, error or arbitration lost).

Bit 3 = RFLM Receive FIFO Locked Mode

Read/set/clear

0: receive FIFO not locked on overrun. Once a receive FIFO is full the next incoming

message will overwrite the previous one.

1: receive FIFO locked against overrun. Once a receive FIFO is full the next incoming

message will be discarded.

Bit 2 = TXFP Transmit FIFO Priority

Read/set/clear

ABOM

AWUM

NART

RFLM

TXFP

SLEEP

INRQ

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