ST72561J4-Auto datasheet(242/324 Pages) STMICROELECTRONICS

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beCAN controller (beCAN)

ST72561-Auto

242/324

Doc ID 12370 Rev 8

CAN receive FIFO registers (CRFR)

Read / write

Reset value: 0000 0000 (00h)

Note:

To clear a bit in this register, software must write a “1” to the bit.

Bits 7:6 = reserved. Forced to 0 by hardware.

Bit 5 = RFOM Release FIFO Output Mailbox

Read/Set

Set by software to release the output mailbox of the FIFO. The output mailbox can only be

released when at least one message is pending in the FIFO. Setting this bit when the FIFO

is empty has no effect. If more than one message are pending in the FIFO, the software has

to release the output mailbox to access the next message.

Cleared by hardware when the output mailbox has been released.

Bit 4 = FOVR FIFO Overrun

Read/ clear

This bit is set by hardware when a new message has been received and passed the filter

while the FIFO was full.

This bit is cleared by software.

Bit 3 = FULL FIFO Full

Read/ clear

Set by hardware when three messages are stored in the FIFO.

This bit can be cleared by software writing a one to this bit or releasing the FIFO by means

of RFOM.

Bit 2 = reserved. Forced to 0 by hardware.

Bits 1:0 = FMP[1:0] FIFO Message Pending

Read

These bits indicate how many messages are pending in the receive FIFO.

FMP is increased each time the hardware stores a new message in to the FIFO. FMP is

decreased each time the software releases the output mailbox by setting the RFOM bit.

CAN Interrupt Enable Register (CIER)

Read/ write

Reset value: 0000 0000 (00h)

Note:

All bits of this register are set and cleared by software.

RFOM

FOVR

FULL

FMP1

FMP0

WKUIE

FOVIE0

FFIE0

FMPIE0

TMEIE

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