ST72561J4-Auto datasheet(236/324 Pages) STMICROELECTRONICS

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beCAN controller (beCAN)

ST72561-Auto

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Doc ID 12370 Rev 8

Therefore if: tIT higher level + tIT disable + tIT CAN < 2 x tCAN frame

the application will never wait in the workaround

tIT higher level: This the sum of the duration of all the interrupts with a level strictly higher than

the CAN interrupt level

tIT disable: This is the longest time the application disables the CAN interrupt (or all interrupts)

tIT CAN: This is the maximum duration between the beginning of the CAN interrupt and the

actual location of the workaround

tCAN frame: This is minimum CAN frame duration

Figure 111. Critical window timing diagram

Figure 112. Reception of a sequence of frames

Side-effect of workaround 1

Because the while loop lasts 10 CPU cycles, at high baud rate, it is possible to miss a

dominant state on the bus if it lasts just one CAN bit time and the bus speed is high enough

(see Table 84).

If this happens, we will continue waiting in the while loop instead of releasing the FIFO

immediately. The workaround is still valid because we will not release the FIFO during the

Table 84.

While loop timing

fCPU

Software timing: while loop

Minimum baud rate for possible

missed dominant bit

8 MHz

1.25 µs

800 Kbaud

4 MHz

2.5 µs

400 Kbaud

fCPU

10/fCPU

fCPU/10

A release is not

allowed at this time

Critical window: the received

message is placed in the FIFO

CAN Frame

Acknowledge: last

dominant bit in the frame

Time to test RX pin and to

release the FIFO 4.5µs@4 MHz Time between the end of the

acknowledge and the critical windows

- 6 full CAN bit times + time to the sample point

approx. 13µs @ 500 Kbaud

tCAN frame 1tCAN frame 2tCAN frame 3

FMP

BUS

CPU

tIT disable

tIT higher level

tIT CAN

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