ST72561J4-Auto datasheet(232/324 Pages) STMICROELECTRONICS

232 / 324 page

beCAN controller (beCAN)

ST72561-Auto

232/324

Doc ID 12370 Rev 8

17.5

Interrupts

Two interrupt vectors are dedicated to beCAN. Each interrupt source can be independently

enabled or disabled by means of the CAN Interrupt Enable Register (CIER) and CAN Error

Interrupt Enable register (CEIER).

Figure 108. Event flags and interrupt generation

●

The FIFO interrupt can be generated by the following events:

–

Reception of a new message, FMP bits in the CRFR0 register incremented.

–

FIFO0 full condition, FULL bit in the CRFR0 register set.

–

FIFO0 overrun condition, FOVR bit in the CRFR0 register set.

●

The transmit, error and status change interrupt can be generated by the following

events:

–

Transmit mailbox 0 becomes empty, RQCP0 bit in the CTSR register set.

–

Transmit mailbox 1 becomes empty, RQCP1 bit in the CTSR register set.

–

Error condition, for more details on error conditions please refer to the CAN Error

Status register (CESR).

–

Wake-up condition, SOF monitored on the CAN Rx signal.

17.6

Erroneous access to certain configuration registers can cause the hardware to temporarily

disturb the whole CAN network. Therefore the following registers can be modified by

software only while the hardware is in initialization mode:

CBTR0, CBTR1, CFCR0, CFCR1, CFMR and CDGR registers.

RQCP

TMEIE

CIER

TRANSMIT/

EWGF

EWGIE

EPVF

EPVIE

BOFF

BOFIE

LECIEF

LECIE

ERRIE

FMP

FMPIE

FULL

FFIE

FOVR

FOVIE

FIFO

INTERRUPT

WKUI

WKUIE

TXMB 0

TXMB 1

INTERRUPT

ERROR/

STATUS CHANGE

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