ST72561J4-Auto datasheet(229/324 Pages) STMICROELECTRONICS

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ST72561-Auto

beCAN controller (beCAN)

Doc ID 12370 Rev 8

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Figure 104. CAN error state diagram

17.4.5

Error management

The error management as described in the CAN protocol is handled entirely by hardware

using a Transmit Error Counter (TECR register) and a Receive Error Counter (RECR

detailed information about TEC and REC management, please refer to the CAN standard.

Both of them may be read by software to determine the stability of the network.

Furthermore, the CAN hardware provides detailed information on the current error status in

CESR register. By means of CEIER register and ERRIE bit in CIER register, the software

can configure the interrupt generation on error detection in a very flexible way.

Bus-off recovery

The Bus-Off state is reached when TECR is greater then 255, this state is indicated by

BOFF bit in CESR register. In Bus-Off state, the beCAN acts as disconnected from the CAN

bus, hence it is no longer able to transmit and receive messages.

Depending on the ABOM bit in the CMCR register beCAN will recover from Bus-Off

(become error active again) either automatically or on software request. But in both cases

the beCAN has to wait at least for the recovery sequence specified in the CAN standard

(128 x 11 consecutive recessive bits monitored on CANRX).

MDAR4

MDAR5

MDAR6

MDAR7

Reserved

Table 83.

Receive mailbox mapping (continued)

Offset to receive mailbox base

address (bytes)

ERROR PASSIVE

When TEC or REC > 127

When TEC and REC < 128,

ERROR ACTIVE

BUS OFF

When TEC > 255

When 128 * 11 recessive bits occur:

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