ST72344K2 datasheet(179/247 Pages) STMICROELECTRONICS

179 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

179/247

Bit 1= ITWE3 Interrupt enable on write to Slave 3

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled.

0: Interrupt after write to Slave 3 disabled

1: Interrupt after write to Slave 3 enabled

Bit 0 = ITWE1/2 Interrupt enable on write to Slave 1 or 2

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled software. It is also cleared by hardware when the interface is disabled.

0: Interrupt after write to Slave 1 or 2 disabled

1: Interrupt after write to Slave 1 or 2 enabled

I2C control register 2 (I2C3SCR2)

Reset value: 0000 0000 (00h)

Bits 7:5 = Reserved, must be kept at 0.

Bit 4 = WP2 Write Protect enable for Slave 2

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled (PE=0)

0: Write access to Slave 2 RAM buffer enabled

1: Write access to Slave 2 RAM buffer disabled

Bit 3 = WP1 Write Protect enable for Slave 1

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled (PE=0).

0: Write access to Slave 1 RAM buffer enabled

1: Write access to Slave 1 RAM buffer disabled

Note:

(Applicable for both WP2/ WP1)

Only write operations are disabled/enabled. Read operations are not affected.

If a write operation is attempted, the slave address is acknowledged, the current address

Both the current address and byte count registers are incremented as in normal operation.

No interrupt generated if slave is write protected

BusyW will not be set if slave is write protected

Bit 2 = PE Peripheral enable

This bit is set and cleared by software.

0: Peripheral disabled

1: Slave capability enabled

Note:

To enable the I2C interface, write the CR register TWICE with PE=1, as the first write only

activates the interface (only PE is set).

WP2

WP1

BusyW

B/W

Read / Write

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