ST7MC1K2-Auto datasheet(347/371 Pages) STMICROELECTRONICS

347 / 371 page

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Electrical characteristics

347/371

12.14

10-bit ADC characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 220.

10-bit ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VAREF Analog reference voltage

VDD

fADC

ADC clock frequency

MHz

VAIN

Conversion voltage range(1)

VSSA

VAREF

Ilkg

Input leakage current for analog

input

±1

µA

Negative input leakage current on

analog pins

VIN < VSS, | IIN |< 400µA

on adjacent analog pin

RAIN

External input impedance

see

Figure 158

and

Figure 159

(2)(3)(4)

Ω

CAIN

External capacitor on analog input

fAIN

Variation freq. of analog input

signal

CADC

Internal sample and hold capacitor

tADC

Conversion time (sample+hold)

fCPU = 8 MHz,

fADC =4MHz,

ADSTS bit in MCCBCR

3.5

µs

– Sample capacitor loading time

– Hold conversion time

1/fADC

Conversion time (sample+hold)

fCPU = 8 MHz,

fADC =4MHz,

ADSTS bit in MCCBCR

6.5

µs

– Sample capacitor loading time

– Hold conversion time

1/fADC

RAREF Analog reference input resistor

Ω

When VSSA pins are not available on the pinout, the ADC refer to VSS.

Any added external serial resistor downgrades the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad

capacitance (3pF). A high CPARASITIC value downgrades conversion accuracy. To remedy this, fADC should be reduced.

This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and

decreased to allow the use of a larger serial resistor (RAIN).

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