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ST7FOXU0 bảng dữ liệu(PDF) 72 Page - STMicroelectronics |
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ST7FOXU0 bảng dữ liệu(HTML) 72 Page - STMicroelectronics |
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72 / 123 page  On-chip peripherals ST7FOXU0 72/123 Figure 34. PWM Signal example Output Compare Mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event). The DCR0H must be written first, the output compare function starts only when the DCR0L value is written. When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE bit is set. Note: The output compare function is only available for DCRx values other than 0 (reset value). Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value has not yet been written (in this case, the shadow register will contain the new DCR0H value and the old DCR0L value), then: - If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register (and not DCRx) - if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There is no PWM signal. The compare between DCRx or the shadow register and the timer counter is locked until DCR0L is written. COUNTER t FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh DCR0=FFEh ATR= FFDh fCOUNTER |
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