ST7FOXU0 datasheet(54/123 Pages) STMICROELECTRONICS

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Power saving modes

ST7FOXU0

54/123

As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR

a fixed divider and a programmable prescaler controlled by the AWUPR register. The output

of this prescaler provides the delay time. When the delay has elapsed, the following actions

are performed:

●

the AWUF flag is set by hardware,

●

an interrupt wakes-up the MCU from Halt mode,

●

the main oscillator is immediately turned on and the 256 CPU cycle delay is used to

stabilize it.

After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The

AWU flag and its associated interrupt are cleared by software reading the AWUCSR

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated

by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.

Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run

mode. This connects fAWU_RC to the Input Capture of the 8-bit Lite timer, allowing the

fAWU_RC to be measured using the main oscillator clock as a reference timebase.

Similarities with halt mode

The following AWUFH mode behavior is the same as normal Halt mode:

●

The MCU can exit AWUFH mode by means of any interrupt with exit from Halt

capability or a reset (see Section 8.4: Active-halt and halt modes).

●

When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable

interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

●

In AWUFH mode, the main oscillator is turned off causing all internal processing to be

stopped, including the operation of the on-chip peripherals. None of the peripherals are

clocked except those which get their clock supply from another clock generator (such

as an external or auxiliary oscillator like the AWU oscillator).

●

The compatibility of watchdog operation with AWUFH mode is configured by the

WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction

when executed while the watchdog system is enabled, can generate a watchdog Reset.

Figure 25.

AWUF halt timing diagram

AWUFH interrupt

fCPU

RUN MODE

HALT MODE

256 tCPU

RUN MODE

fAWU_RC

Clear

by software

tAWU

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