SPC56EL70L3 datasheet(26/128 Pages) STMICROELECTRONICS

26 / 128 page

Introduction

SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

26/128

DocID023953 Rev 5

A FlexPWM module implements the following features:



16 bits of resolution for center, edge aligned, and asymmetrical PWMs



Maximum operating frequency as high as 120 MHz

–

Clock source not modulated and independent from system clock (generated via

secondary FMPLL)



Fine granularity control for enhanced resolution of the PWM period



PWM outputs can operate as complementary pairs or independent channels



Ability to accept signed numbers for PWM generation



Independent control of both edges of each PWM output



Synchronization to external hardware or other PWM supported



Double buffered PWM registers

–

Integral reload rates from 1 to 16

–

Half cycle reload capability



Multiple ADC trigger events can be generated per PWM cycle via hardware



Fault inputs can be assigned to control multiple PWM outputs



Programmable filters for fault inputs



Independently programmable PWM output polarity



Independent top and bottom deadtime insertion



Each complementary pair can operate with its own PWM frequency and deadtime

values



Individual software control for each PWM output



All outputs can be forced to a value simultaneously



PWMX pin can optionally output a third signal from each channel



Channels not used for PWM generation can be used for buffered output compare

functions



Channels not used for PWM generation can be used for input capture functions



Enhanced dual edge capture functionality



Option to supply the source for each complementary PWM signal pair from any of the

following:

–

External digital pin

–

Internal timer channel

–

External ADC input, taking into account values set in ADC high- and low-limit

registers



DMA support

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