SPC56EL70L3 datasheet(105/128 Pages) STMICROELECTRONICS

105 / 128 page

DocID023953 Rev 5

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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

Electrical characteristics

127

Figure 17. Functional Reset Sequence Short

The reset sequences shown in Figure 16 and Figure 17 are triggered by functional reset

events. RESET is driven low during these two reset sequences only if the corresponding

functional reset source (which triggered the reset sequence) was enabled to drive RESET

low for the duration of the internal reset sequence(c).

3.19.3

Reset sequence trigger mapping

The following table shows the possible trigger events for the different reset sequences. It

specifies the reset sequence start conditions as well as the reset sequence end indications

that are the basis for the timing data provided in Table 31.

PHASE3

DRUN

Application

Execution

TFRS, min < TReset < TFRS, max

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

RESET

c. See RGM_FBRE register for more details.

Table 32. Reset sequence trigger — Reset sequence

Reset

Sequence

Trigger

Reset

Sequence

Start

Condition

Reset

Sequence

End

Indication

Reset Sequence

Destructive

reset

sequence,

bist

enabled(1)

Destructive

reset

sequence,

bisT

disabled(1)

External

reset

sequence

long, bIST

enabled

Functional

reset

sequence

long

Functional

reset

sequence

short

All internal

destructive reset

sources

(LVDs or internal

HVD during

power-up and

during operation)

Section 3.19.

4.1:

Destructive

reset

Release of

RESET(2)

triggers

cannot

trigger

cannot

trigger

cannot

trigger

Assertion of

RESET(3)

Section 3.19.

4.2: External

reset via

RESET

cannot trigger

triggers(4)

triggers(5)

triggers(6)

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