LNBH24 software description

LNBH24L

16/25

Doc ID 16857 Rev 2

X = don't care

Values are typical unless otherwise specified

Valid with TTX pin floating

7.4

Diagnostic received data (I²C read mode) for both sections

A/B

The LNBH24L can provide to the MCU master a copy of the diagnostic system register

information via I²C bus in read mode. The read mode is master activated by sending the

chip address with R/W bit set to 1. At the following master generated clocks bits, LNBH24L

issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the

master can:

●

Acknowledge the reception, starting in this way the transmission of another byte from

the LNBH24L

●

No acknowledge, stopping the read mode communication

Three bits of the register are read back as a copy of the corresponding write output voltage

register status (LLC, VSEL, EN), two bits convey diagnostic information about the over-

temperature (OTF), output over-load (OLF) and three bit are for internal usage (TEST1-2-3)

and must be disregarded by the MCU software. In normal operation the diagnostic bits are

set to zero, while, if a failure is occurring, the corresponding bit is set to one. At start-up all

the bits are reset to zero.

Table 7.

Truth table

PCL

TTX

TEN

LLC

VSEL

EN

TEST4 TEST5

Function

00

0

1

0

0

00

1

1

0

0

01

0

1

0

0

01

1

1

0

0

10

1

0

0

Internal 22 kHz controlled by DSQIN pin (only if

TTX=1)

11

1

0

0

activated

00

1

0

0

Internal 22 kHz generator disabled, EXTM

modulation enabled

01

0

0

OFF

11

0

0

ON

0

1

0

0

Pulsed (Dynamic) current limiting is selected

1

1

0

0

Static current limiting is selected

X

X

X

X

X

0

X

X

Power block disabled