LNBH24L

LNBH24 software description

Doc ID 16857 Rev 2

15/25

7

LNBH24 software description

The LNBH24L I²C interface controls both the IC sections A and B depending on the address

sent before the DATA byte. All the below description is valid for both sections.

7.1

Interface protocol

The interface protocol comprises:

●

A start condition (S)

●

A chip address byte [the LSB bit determines read (=1)/write (=0) transmission]

●

A sequence of data (1 byte + acknowledge)

●

A stop condition (P)

ACK = Acknowledge

S = Start

P = Stop

R/W = 1/0, Read/Write bit

X = 0/1, two addresses for each section selectable by ADDR-A/B pins (see Table 11)

7.2

System register (SR, 1 Byte for each section A and B)

Write = control bits functions in write mode

Read = diagnostic bits in read mode.

All bits reset to 0 at power on

7.3

Transmitted data (I²C bus write mode) for each sections A/B

When the R/W bit in the section address is set to 0, the main microprocessor can write on

the system register (SR) of the relative section (A or B, depending on the 7 bit address

value) via I²C bus. All and 8 bits are available and can be written by the microprocessor to

control the device functions as per the below truth table (Table 7).

Section address (A or B)

Data

MSB

LSB

MSB

LSB

S

0

0

0

1

0

X

X

R/W ACK

ACK

P

Mode

MSB

LSB

Write

PCL

TTX

TEN

LLC

VSEL

EN

TEST4

TEST5

Read

TEST1

TEST2

TEST3

LLC

VSEL

EN

OTF

OLF