ST1S50 datasheet(18/29 Pages) STMICROELECTRONICS

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Application information

ST1S50

18/29

DocID025723 Rev 4

6.4

Compensation network selection

The compensation network must be chosen to have a phase margin higher than 45° given

the application condition (VIN, VOUT, L, COUT) and the requested bandwidth. The larger is

the bandwidth, the faster is the loop response to the load transient. Maximum allowed

bandwidth is one fourth/fifth of the switching frequency (that is 100 - 120 kHz).

Figure 7. Compensation network

Starting from the target bandwidth (fBW) the compensation network values can be calculated

to have a stable loop response basing Equation 22 and Equation 23.

Given the target bandwidth fBW, the resistor RC results:

Equation 22

where COUT is the output capacitor (actual value properly derated according to the applied

DC voltage), Ri is the equivalent sensing resistor of the current sense circuitry (0.3 V/A), Gm

is the error amplifier trans-conductance (250

S) and VREF is the internal reference, 0.8 V.

The capacitor CC has to be designed to place the zero of the compensation network (fZ) at

the frequency of the power stage pole (fP 1 / (2RLOADCOUT)).

Equation 23

The capacitor CP is optional and it can be used to cancel the zero from the ESR of the

output capacitor.

The capacitor CF can be used to have phase boost adding a further zero close to the

crossover frequency. CF inserts also a pole at very high frequency, usually negligible. The

phase boost effect decreases as the VOUT decreases.

VREF E/A

optional

VOUT

 f

BW VOUT COUT Ri





Gm VREF



----------------------------------------------------------------------

RLOAD C



OUT

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