STSPIN32F0 datasheet(24/40 Pages) STMICROELECTRONICS

tên linh kiện	STSPIN32F0

Giải thích chi tiết về linh kiện	Three-phase gate drivers

PDF	40 Pages

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Device description

STSPIN32F0

24/40

DocID029806 Rev 2

Figure 11. “Standby to normal” operation timing (CREG = 1 µF)

Equation 1

6.5

Gate drivers

The STSPIN32F0 device integrates a triple half-bridge gate driver able to drive N-channel

power MOSFETs or IGBTs. The high-side section is supplied by a bootstrapped voltage

technique with an integrated bootstrap diode.

All the input lines (refer to Figure 2: Analog IC block diagram on page 6) are connected to

a pull-down resistor (60 k

 typical value) to guarantee the low logic level during the device

start-up.

The high- and low-side outputs of same half-bridge cannot be simultaneously driven high

thanks to an integrated interlocking function.

Note:

All the input lines of the analog IC have an internal pull-down to guarantee the low logic level

during the device start-up and when the MCU lines are not present.

tREG

CREG VREG12



IREG12 lim



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STSPIN32F0 bảng dữ liệu(PDF) 24 Page - STMicroelectronics