ASP0905 datasheet(67/128 Pages) TI1

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MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526

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SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015

6.9.21 Peripheral File Map

Table 6-15 lists the base address for the registers of each module. The following tables list the offsets for

all available registers in each module.

Table 6-15. Peripherals

OFFSET ADDRESS

MODULE NAME

BASE ADDRESS

RANGE

Special Functions (see Table 6-16)

0100h

000h-01Fh

PMM (see Table 6-17)

0120h

000h-010h

Flash Control (see Table 6-18)

0140h

000h-00Fh

CRC16 (see Table 6-19)

0150h

000h-007h

RAM Control (see Table 6-20)

0158h

000h-001h

Watchdog (see Table 6-21)

015Ch

000h-001h

UCS (see Table 6-22)

0160h

000h-01Fh

SYS (see Table 6-23)

0180h

000h-01Fh

Shared Reference (see Table 6-24)

01B0h

000h-001h

Port Mapping Control (see Table 6-25)

01C0h

000h-002h

Port Mapping Port P4 (see Table 6-25)

01E0h

000h-007h

Port P1 and P2 (see Table 6-26)

0200h

000h-01Fh

Port P3 and P4 (see Table 6-27)

0220h

000h-00Bh

Port P5 and P6 (see Table 6-28)

0240h

000h-00Bh

Port P7 and P8 (see Table 6-29)

0260h

000h-00Bh

Port PJ (see Table 6-30)

0320h

000h-01Fh

TA0 (see Table 6-31)

0340h

000h-02Eh

TA1 (see Table 6-32)

0380h

000h-02Eh

TB0 (see Table 6-33)

03C0h

000h-02Eh

TA2 (see Table 6-34)

0400h

000h-02Eh

Real-Time Clock (RTC_A) (see Table 6-35)

04A0h

000h-01Bh

32-Bit Hardware Multiplier (see Table 6-36)

04C0h

000h-02Fh

DMA General Control (see Table 6-37)

0500h

000h-00Fh

DMA Channel 0 (see Table 6-37)

0510h

000h-00Ah

DMA Channel 1 (see Table 6-37)

0520h

000h-00Ah

DMA Channel 2 (see Table 6-37)

0530h

000h-00Ah

USCI_A0 (see Table 6-38)

05C0h

000h-01Fh

USCI_B0 (see Table 6-39)

05E0h

000h-01Fh

USCI_A1 (see Table 6-40)

0600h

000h-01Fh

USCI_B1 (see Table 6-41)

0620h

000h-01Fh

ADC12_A (see Table 6-42)

0700h

000h-03Eh

Comparator_B (see Table 6-43)

08C0h

000h-00Fh

USB Configuration (see Table 6-44)

0900h

000h-014h

USB Control (see Table 6-45)

0920h

000h-01Fh

Detailed Description

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