ASP0905 datasheet(49/128 Pages) TI1

49 / 128 page

MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526

MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521

MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513

www.ti.com

SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015

5.48 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

DVCC(PGM,ERASE) Program and erase supply voltage

1.8

3.6

IPGM

Average supply current from DVCC during program(1)

IERASE

Average supply current from DVCC during erase(1)

Average supply current from DVCC during mass erase or bank

IMERASE, IBANK

erase(1)

tCPT

Cumulative program time

See (2)

Program and erase endurance

104

105

cycles

tRetention

Data retention duration

TJ = 25°C

100

years

tWord

Word or byte program time

See (3)

µs

tBlock, 0

Block program time for first byte or word

See (3)

µs

Block program time for each additional byte or word, except for last

tBlock, 1–(N–1)

See (3)

µs

byte or word

tBlock, N

Block program time for last byte or word

See (3)

µs

Erase time for segment, mass erase, and bank erase when

tErase

See (3)

available.

MCLK frequency in marginal read mode

fMCLK,MRG

MHz

(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)

(1)

Default clock system frequency of MCLK = 1 MHz, ACLK = 32768 Hz, SMCLK = 1 MHz. No peripherals are enabled or active.

(2)

The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word- or byte-write and block-write modes.

(3)

These values are hardwired into the state machine of the flash controller.

5.49 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

fSBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse duration

2.2 V, 3 V

0.025

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

tSBW, En

2.2 V, 3 V

µs

edge)(1)

tSBW,Rst

Spy-Bi-Wire return to normal operation time

100

µs

2.2 V

fTCK

TCK input frequency, 4-wire JTAG(2)

MHz

3 V

Rinternal

Internal pulldown resistance on TEST

2.2 V, 3 V

(1)

Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2)

fTCK may be restricted to meet the timing requirements of the module selected.

Specifications

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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513

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