DM368ZCEZ datasheet(9/208 Pages) TI1

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ARM926EJ-S

16KI$

8KD$

MMU

CP15

Arbiter

I-AHB

D-AHB

Master

I-TCM

D-TCM

16K

RAM0

RAM1

16K

ROM

16K

Arbiter

Slave

MasterIF

ARM

Interrupt

Controller

(AINTC)

Control

System

PLLC2

PLLC1

(PSC)

Controller

Sleep

Power

Peripherals

...

TMS320DM368

www.ti.com

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

Figure 2-1. ARM Subsystem Block Diagram

2.3.2

ARM926EJ-S RISC CPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of

ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications

where full memory management, high performance, low die size, and low power are all important. The

ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to

trade off between high performance and high code density. Specifically, the ARM926EJ-S processor

supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,

providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code

overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a

complete high performance subsystem, including:

•

ARM926EJ -S integer core

•

CP15 system control coprocessor

•

Memory Management Unit (MMU)

•

Separate instruction and data Caches

•

Write buffer

•

Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces

•

Separate instruction and data AHB bus interfaces

•

Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com

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