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ASP00886IRGCR bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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ASP00886IRGCR bảng dữ liệu(HTML) 1 Page - Texas Instruments |
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1 / 128 page ![]() Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526 MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513 SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015 MSP430F552x, MSP430F551x Mixed-Signal Microcontrollers 1 Device Overview 1.1 Features 1 – Low-Frequency Trimmed Internal Reference • Low Supply Voltage Range: Source (REFO) 3.6 V Down to 1.8 V – 32-kHz Watch Crystals (XT1) • Ultra-Low Power Consumption – High-Frequency Crystals up to 32 MHz (XT2) – Active Mode (AM): • 16-Bit Timer TA0, Timer_A With Five • All System Clocks Active: Capture/Compare Registers – 290 µA/MHz at 8 MHz, 3.0 V, Flash • 16-Bit Timer TA1, Timer_A With Three Program Execution (Typical) Capture/Compare Registers – 150 µA/MHz at 8 MHz, 3.0 V, RAM • 16-Bit Timer TA2, Timer_A With Three Program Execution (Typical) Capture/Compare Registers – Standby Mode (LPM3): • 16-Bit Timer TB0, Timer_B With Seven • Real-Time Clock (RTC) With Crystal, Capture/Compare Shadow Registers Watchdog, and Supply Supervisor • Two Universal Serial Communication Interfaces Operational, Full RAM Retention, Fast Wake – USCI_A0 and USCI_A1 Each Support: up: • Enhanced UART Supports Automatic Baud- – 1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) Rate Detection • Low-Power Oscillator (VLO), General- • IrDA Encoder and Decoder Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, • Synchronous SPI Fast Wake up: – USCI_B0 and USCI_B1 Each Support: – 1.4 µA at 3.0 V (Typical) • I2C – Off Mode (LPM4): • Synchronous SPI • Full RAM Retention, Supply Supervisor • Full-Speed Universal Serial Bus (USB) Operational, Fast Wake up: – Integrated USB-PHY – 1.1 µA at 3.0 V (Typical) – Integrated 3.3-V and 1.8-V USB Power System – Shutdown Mode (LPM4.5): – Integrated USB-PLL • 0.18 µA at 3.0 V (Typical) – Eight Input and Eight Output Endpoints • Wake up From Standby Mode in 3.5 µs (Typical) • 12-Bit Analog-to-Digital Converter (ADC) • 16-Bit RISC Architecture, Extended Memory, up to (MSP430F552x Only) With Internal Reference, 25-MHz System Clock Sample-and-Hold, and Autoscan Feature • Flexible Power Management System • Comparator – Fully Integrated LDO With Programmable • Hardware Multiplier Supports 32-Bit Operations Regulated Core Supply Voltage • Serial Onboard Programming, No External – Supply Voltage Supervision, Monitoring, and Programming Voltage Needed Brownout • Three-Channel Internal DMA • Unified Clock System • Basic Timer With RTC Feature – FLL Control Loop for Frequency Stabilization • Section 3 Summarizes Available Family Members – Low-Power Low-Frequency Internal Clock • For Complete Module Descriptions, See the Source (VLO) MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) 1.2 Applications • Analog and Digital Sensor Systems • Connection to USB Hosts • Data Loggers 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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