TFP201, TFP201A

TI PanelBus DIGITAL RECEIVER

SLDS116A - MARCH 2000 – REVISED JUNE 2000

12

POST OFFICE BOX 655303

detailed description (continued)

TFP201/201A TMDS input levels and input impedance matching (continued)

_

+

Internal

Termination at 50

Ω

AVDD

DVI Compliant Cable

DATA

DATA

TI TFP201/201A

Receiver

DVI

Transmitter

Current

Source

Figure 14. TMDS Differential Input and Transmitter Connection

1/2 VIDIFF

AVCC

AVCC - 1/2 VIDIFF

+ 1/2 VIDIFF

- 1/2 VIDIFF

VIDIFF

a ) Single-Ended Input Signal

b) Differential Input Signal

Figure 15. TMDS Inputs

TFP201A incorporates HSYNC jitter immunity

Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals

during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal

in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver,

and if the position of HSYNC shifts continuously, the receiver can lose track of the input timing and pixel noise

will occur on the display. For this reason, a DVI compliant receiver with HSYNC jitter immunity should be used

in all displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem.

The TFP201A integrates HSYNC regeneration circuitry that provides a seamless interface to these

noncompliant transmitters. The position of the data enable (DE) signal is always fixed in relation to data,

irrespective of the location of HSYNC. The TFP201A receiver uses the DE and clock signals recreate stable

vertical and horizontal sync signals. The circuit filters the HSYNC output of the receiver, and HSYNC is shifted

to the nearest eighth bit boundary, producing a stable output with respect to data, as shown in Figure 16. This

will ensure accurate data synchronization at the input of the display timing controller.