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PC87570 bảng dữ liệu(PDF) 46 Page - National Semiconductor (TI) |
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PC87570 bảng dữ liệu(HTML) 46 Page - National Semiconductor (TI) |
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46 / 168 page ![]() Bus Interface Unit (BIU) 46 www.national.com Bit 9 - Post Idle (IPST) An idle cycle follows the current bus cycle, when the next bus cycle is in a different zone . 0: No idle cycle inserted 1: Idle cycle inserted Bit 10 - Preliminary Idle ((IPR) An idle cycle is inserted prior to the current bus cycle, when this bus cycle is in a new zone . 0: No idle cycle inserted 1: Idle cycle inserted Bit 11 - Fast Read Enable (FRE) FRE enables fast read bus cycles. 0: Fast read bus cycle disabled. Read bus cycle takes at least two clock cycles (i.e., Normal Read bus cycle). 1: Fast read bus cycle enabled. Read bus cycle takes one clock cycle. 3.6 USAGE HINTS The following usage hints will help you configure the BIU to max- imize PC87570 performance while avoiding contention on the data bus. 1. In IRE environment, the access time to the internal ROM can use zero wait and zero hold cycles, but not fast reads. Therefore, program SZCFG1 fields as follows: WAIT=000, HOLD=00, BRE=0, WBE=0, BW=1, FRE=0 (where BRE, WBE, BW and FRE are defaults). 2. To avoid data bus contention when a read bus cycle (no Thold clock cycles) in one zone is followed by a read bus cycle in another zone, program IPST and IPRE in the different memory (I/O) zones as follows: Note: When running boot code (zone 1) in IRE environ- ment using the above configuration, performance is much more efficient than in non-IRE environments. However, this configuration is not valid in non-IRE environments. Environment I/O Expansion Configuration IRE Not used Clear IPST and IPRE in all zones IRE Used Clear IPST and IPRE in all zones, except IOCFG.IPST=1 (default) Non-IRE Don’t care Clear IPST and IPRE in all zones, except SZCFG1.IRE=1 SZCFG.IPST=1 and IOCFG.IPST=1 (defaults) |
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