PC87570 datasheet(27/168 Pages) NSC

27 / 168 page

Signal/Pin Connection and Description

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2.4.3

System Load on Strap Pins

The loads connected to the strap pins should prevent the

voltage on them from dropping below VSTRh when the pins

should be high (1), or rising above VSTRl when they should

be low (0). See Table 19-7 on page 135.

If the load caused by the system on the strap pins exceeds

µA when V

CC = 5.0V or 5 µA when VCC = 3.3V, use ei-

ther an external pull-up resistor or a smaller pull-down resis-

tor to keep the pin at 1 or 0, respectively.

2.4.4

Strap Inputs During Idle Mode

When the PC87570 is in Idle mode and shared memory with

host BIOS is enabled, the A(16-18) signals are forced to the

value sampled on the strap input that shares the pin. This is

done to reduce leakage currents on external resistors con-

nected to that pin.

Note: A(16-17) are reserved strap inputs that should not

be pulled to 1.

2.4.5

Strap Pin Status Register (STRPST)

The STRPST Register is a byte-wide, read-only register. It

enables the software to read the value set to strap pins dur-

ing power-up reset. STRPST bits provide the value of their

respective strap input. See Table 2-5 for bit details.

2.5

ALTERNATE FUNCTIONS

The PC87570 uses the GPIO port pins to multiplex func-

tions and thereby maximize the device’s flexibility, as

shown in Table 2-5. You select alternate pin functions

through the configuration registers and strap options, as fol-

lows:

The SHBM strap pin (see Table 2-4) controls the PA

pins. When SHBM = 1, the pins function as GPIO port

signals. When SHBM=0, they function as described in

Section 5.2.1 on page 49.

The ports’ Alternate Function Control Register controls

the PB, PC, PD and PE pins. Each of the ports’ pins

may be used as a GPIO port or in its alternate function.

The environment setting and MCFG bits control port

PF and PG pins.

The environment setting controls port PH pins. When

in Dev environment, the pins perform their alternate

functions. In IRE or IRD environments, they function

as GPIO ports.

When a pin is used as GPIO and not in its alternate function,

disable the alternate function in the module’s register to pre-

vent wired effects.

Table 2-5 lists the I/O pins and their alternate functions.

When you use a pin as GPIO, you should disable the alter-

nate function in the module register to prevent wired effects.

Table 2-5. Alternate Function Mapping

HDEN Disables host interface;

must be enabled using

the motherboard PnP

protocol after each reset

Enables host interface

to its default settings

(legacy address of KBC,

RTC and PMC)

TRIS Normal operation

Causes PC87570 to

ﬂoat all its output and

I/O signals for ISE use

Strap

Internal Pull-Down (0)

External Pull-Up (1)

Reserved

HDEN

HRMS

SHBM

Pin Name

Port Signal

Alternate

Function

Select

(Alternate Function)

Name

Type

PA0/HMEMCS

PA0

I/O

HMEMCS

SHBM=0

PA1/HMEMRD

PA1

HMEMRD

PA2/HMEMWR

PA2

HMEMWR

PA3/HA16

PA3

HA16

PA4/HA17

PA4

HA17

PA5/A16

PA5

A16

PA6/A17

PA6

A17

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