PC87366-XXXSLASHVLA datasheet(79/240 Pages) NSC

79 / 240 page

2.0 Device Architecture and Configuration (Continued)

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2.20 MIDI PORT (MIDI) CONFIGURATION

2.20.1

Logical Device 12 (MIDI) Configuration

Table 34 lists the configuration registers which affect the MIDI Port. Only the last register (F0h) is described here. See Sec-

tions 2.2.3 and 2.2.4 for a detailed description of the others.

Table 35. MIDI Conﬁguration Registers

2.20.2

MIDI Port Configuration Register

This register is reset by hardware to 00h.

Location:

Index F0h

Type:

R/W

Usage Hint:

To operate MIDI enhanced features, make sure to locate its base address within the LPC Wide Generic address range.

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h

Base Address MSB register

R/W

03h

61h

Base Address LSB register. Bits 2-0 (for A2-A0) are read only, 000b.

R/W

30h

70h

Interrupt Number and wake-up on IRQ enable.

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

MIDI Port Conﬁguration register

R/W

00h

Bit

76543210

Name

Reserved

Internal

Pull-Up

Enable

Reserved

TRI-STATE

Control

Reset

00000000

Bit

Description

7-3

Reserved

Internal Pull-Up Enable. This bit controls the internal pull-up resistor on pin 126 (GPIO31/MDRX).

0: Disabled (default)

1: Enabled

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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