PC87366-XXXSLASHVLA datasheet(37/240 Pages) NSC

37 / 240 page

2.0 Device Architecture and Configuration (Continued)

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Write accesses to unimplemented registers (i.e. accessing the Data register while the Index register points to a non-existing

returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.

2.2.3

Standard Logical Device Configuration Register Definitions

Unless otherwise noted in Tables 7 through 12:

All registers are read/write.

All reserved bits return 0 on reads, except where noted otherwise. They must not be modiﬁed as it may cause un-

predictable results. Use read-modify-write to prevent the values of reserved bits from being changed during write.

Write only registers should not use read-modify-write during updates.

Table 7. Standard Control Registers

Table 8. Logical Device Activate Register

Table 9. I/O Space Conﬁguration Registers

Index

Description

07h

Logical Device

Number

This register selects the current logical device. See Table 6 for valid numbers. All

other values are reserved.

20h - 2Fh

SuperI/O

Conﬁguration

SuperI/O conﬁguration registers and ID registers

Index

Description

30h

Activate

Bit 0 - Logical device activation control

0: Disabled

1: Enabled

Bits 7-1 - Reserved

Index

Description

60h

I/O Port Base

Address Bits (15-8)

Descriptor 0

Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0.

61h

I/O Port Base

Address Bits (7-0)

Descriptor 0

Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0.

62h

I/O Port Base

Address Bits (15-8)

Descriptor 1

Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 1.

63h

I/O Port Base

Address Bits (7-0)

Descriptor 1

Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 1.

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