PC87366 datasheet(129/240 Pages) NSC

129 / 240 page

5.0 Fan Speed Monitor (Continued)

129

www.national.com

5.4

FAN SPEED MONITOR BITMAP

Bit

Type

Description

Reserved

6-5

R/W Clock Select. Selects the clock source provided to the counter.

These bits must not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled).

00:

16 KHz

01:

8 KHz (default)

10:

4 KHz

11:

2 KHz

R/W Filter Disable. When this bit is set to 1, the digital ﬁlter is disabled. When it is cleared, the ﬁlter is

enabled. This bit should not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled)

to avoid unpredictable results.

0: Digital ﬁlter enabled (default)

1: Digital ﬁlter disabled

R/W Interrupt Enable. This bit controls the assertion of overﬂow interrupt and Over Threshold interrupt.

0: Interrupt disabled (default)

1: Interrupt enabled. Interrupt is asserted when an Over Threshold bit, Overﬂow bit or both are set to 1.

R/W1C Overﬂow. Indicates that the counter has passed FFh, and the fan speed is inefﬁciently slow; i.e., slower

than 60

∗ f/(256 ∗ n). Writing 1 to this bit clears it to 0.

0: No overﬂow occurred since the last time this bit was cleared (by reset or by writing 1)

1: Counter passed FFh

R/W1C Over Threshold. Indicates that the value loaded into the FMSPR register upon detection of the rising

edge of the FANIN pulse exceeded the threshold value.

0: FMSPR register value did not exceed the threshold since the last time this bit was cleared (by reset

or by writing 1)

1: FMSPR register value exceeded the threshold

0RO

Speed Ready. This bit indicates that the speed register holds new (not yet read) and valid data. It is set

to 1 on each rising edge of the FANIN input (starting from the second one) if the Over Threshold bit is

0. It is cleared to 0 whenever the speed register is read, or when the Overflow bit is set.

0: No new valid data in the FMSPR register (data is either invalid or has already been read)

1: FMSPR register loaded with new and valid data

Bits

Offset

Mnemonic

43210

Device

speciﬁc

Note 1.

Note 1. The location of this register is deﬁned in the

Device Architecture and Conﬁguration chapter.

FMTHR

Threshold Value

Device

speciﬁc

Note 1.

FMSPR

Fan Speed Reading

Device

speciﬁc

Note 1.

FMCSR

Reserved

Clock Select

Filter

Disable

Interrupt

Enable

Overﬂow

Over

Threshold

Speed

Ready

PC87366 bảng dữ liệu(PDF) 129 Page - National Semiconductor (TI)

PC87366 bảng dữ liệu(HTML) 129 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL