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6.0

General-Purpose Input/Output (GPIO) Port

This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.

For the device specific implementation, see the

Device Architecture and Configuration chapter.

6.1

OVERVIEW

The GPIO port is an 8-bit port, which is based on eight pins. It features:

Software capability to manipulate and read pin levels

Controllable system notiﬁcation by several means based on the pin level or level transition

Ability to capture and manipulate events and their associated status

Back-drive protected pins.

GPIO port operation is associated with two sets of registers:

Pin Conﬁguration registers, mapped in the Device Conﬁguration space. These registers are used to statically set up

the logical behavior of each pin. There are two 8-bit register for each GPIO pin.

Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and

GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by

the base address registers in the GPIO Device Conﬁguration). They are used to manipulate and/or read the pin val-

ues, and to control and handle system notiﬁcation. Each runtime register corresponds to the 8-pin port, such that bit

n in each one of the four registers is associated with GPIOXn pin, where X is the port number.

Each GPIO pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as

shown in Figure 17.

The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO

pins, and enhanced functionality. The basic functionality is described in Section 6.2. The enhanced functionality which in-

cludes the event detection and system notification is described in Section 6.3.

Figure 17. GPIO Port Architecture

GPIO Pin

Select (GPSEL)

Conﬁguration (GPCFG)

GPDOX

GPDIX

GPEVENX

GPSTX

Runtime

Registers

GPIOX Base Address

Event

Bit n

Port and Pin

8 GPCFG

Registers

GPIOXn

GPIOXn CNFG

Interrupt

GPIOXn

Port Logic

X = port number

n = pin number, 0 to 7

Pending

Indicator

Request

SMI

PWUREQ

GPIO Pin Event

Routing (GPEVR)

8 GPEVR

Registers

GPIOXn ROUTE

Select

Event

Routing

Control

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