STGAP1S datasheet(38/67 Pages) STMICROELECTRONICS

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Functional description

STGAP1S

38/67

DocID027190 Rev 3

To ensure the check result, some applicative conditions have to be verified:

–

The bleeding resistor, sometimes present between the gate and source in the

power switch, shall be lower than 8.2 k

.

–

During the test, the power switch gate shall have the time to be charged up to

VCLAMPth by IGOFFchk. In case no bleeding resistor is present, this time can be

roughly computed as:

tGATE_GOFFchk ≈ CGATE * (VCLAMPth - VL) / IGOFFchk

If a bleeding resistor is present or an additional push-pull circuit has been added,

the time has to be computed with the adequate corrective factors.

If the check fails due to the lack of the GOFF resistor, the power switch gate will gradually

rise up to VH with no protections of SENSE nor DESAT. The user test routine shall consider

this behavior.

Figure 17. Gate paths check circuitry

Floating

Section

Control

Logic

Floating ground

GON

GOFF

CLAMP

GNDISO

VCLAMPth

Level

Shifter

SDO

SDI

SPI

Control

Logic

IGOFFchk

VH testcontrol

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