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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PC97338VLJ bảng dữ liệu(PDF) 205 Page - National Semiconductor (TI) |
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PC97338VLJ bảng dữ liệu(HTML) 205 Page - National Semiconductor (TI) |
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205 / 221 page  205 www.national.com FDRT — FIR Data Rate Tolerance. Percent of Nominal Data Rate. Transmitter +/- 0.01% Receiver +/- 0.01% tFJT — FIR Leading Edge Jitter. Percent of Nominal Chip Duration. Transmitter +/- 4.0% Receiver +/- 25.0% tFPW Figure 96 FIR Single Pulse Width (Note 6) Transmitter 115 135 ns Receiver, Leading Edge Jitter = 0 ns 80 175 ns Receiver, Leading Edge Jitter = +/- 25 ns 90 150 ns tDPW Figure 96 FIR Double Pulse Width (Note 6) Transmitter 115 135 ns Receiver, Leading Edge Jitter = 0 ns 205 300 ns Receiver, Leading Edge Jitter = +/- 25 ns 215 310 ns tWOD Figure 97 RTS, DTR and IRSLn Output Delay From Write Inactive 40 ns tMDO Figure 98 Delay from WR (WR MCR) to output. 40 ns tHL Figure 98 RI2, 1 High-to-Low Transition 10 ns tRIM Figure 98 Delay to Reset IRQ From RD (MSR) 78 ns tSIM Figure 98 Delay to Reset IRQ From Modem Input 40 ns FLOPPY DISK CONTROLLER TIMING tHDS Figure 99 HDSEL Signal Setup 100 µs tHDH Figure 99 HDSEL Signal Hold 750 µs tWDW Figure 99 1 Mbps 250 ns 500 kbps 250 ns 300 kbps 375 ns 250 kbps 500 ns tDRV Figure 101 DR3-0, MTR3-0 Signals Delay from WR Inactive 110 ns tDST Figure 101 DIR Signal Setup to STEP Active 6 µs tIW Figure 101 Index Pulse Width 100 ns tSTR Figure 101 STEP Signal Rate Time (See Table 3-2) 1 ms tSTP Figure 101 STEP Signal Pulse Width 8 µs tSTD Figure 101 DIR Signal Hold From STEP Inactive tSTR ms tRDW Figure 100 Read Data Signal Pulse Width 50 ns PARALLEL PORT TIMING ( COMPATIBLE AND EXTENDED MODES) tPIB Figure 103 Parallel Port Interrupt Active 33 ns tPIE Figure 103 Parallel Port Interrupt Inactive 33 ns tBLSL Figure 104 BUSY Signal Low to STB Low 0 ns Symbol Figure Parameter Min Max Unit |
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