PC97338VLJ datasheet(100/221 Pages) NSC

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3.6.5

The INVALID Command

If an invalid command (illegal opcode byte in the com-

mand phase) is received by the Floppy Disk Control-

ler (FDC), the controller responds with the result

phase Status register 0 (ST0) in the result phase. See

“Result Phase Status Register 0 (ST0)” on page 88

The controller does not generate an interrupt during

this condition. Bits 7 and 6 in the MSR (see Section

3.3.6 page 80) are both set to 1, indicating to the mi-

croprocessor that the controller is in the result phase

and the contents of ST0 must be read.

Command Phase

Execution Phase

None.

Result Phase

The system reads 80 (hex) from ST0 indicating that

an invalid command was received.

3.6.6

The LOCK Command

The LOCK command can be used to keep the FIFO

enabled and to retain the values of some parameters

after a software reset.

After the command byte of the LOCK command is

written, its result byte must be read before the opcode

of the next command can be read. The LOCK com-

mand is not executed until its result byte is read by the

microprocessor.

If the part is reset after the command byte of the

LOCK command is written but before its result byte is

read, then the LOCK command is not executed. This

prevents accidental execution of the LOCK com-

mand.

Command Phase

Bit 7 - Control Reset Effect (LOCK)

This bit determines how the FIFO, THRESH, and

PRETRK bits in the CONFIGURE command and,

the FWR, FRD, and BST bits in the MODE com-

mand are affected by a software reset.

0 -Set default values after a software reset. (De-

fault)

1 - Values are unaffected by a software reset.

Execution Phase

Internal register is written.

Result Phase

Bit 4 - Control Reset Effect (LOCK)

Same as bit 7 of opcode in command phase.

7654

3210

Invalid Opcodes

7654

3210

Result Phase Status Register 0 (STO) (80 hex)

7654

3210

LOCK

001

0100

7654

3210

000

LOCK

0000

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