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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PC97338VLJ bảng dữ liệu(PDF) 203 Page - National Semiconductor (TI) |
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PC97338VLJ bảng dữ liệu(HTML) 203 Page - National Semiconductor (TI) |
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203 / 221 page  203 www.national.com 8.4 SWITCHING CHARACTERISTICS All the timing specifications given in this section refer to 0.8V and 2.0V on all the signals as illustrated in Figure 90, unless specifically stated otherwise. FIGURE 90. Testing Specification Standard 8.4.1 Timing Table TA = 0°C to 70°C, VDD = 5V +/- 10% or 3.3V +/- 10%, VSS = 0V Symbol Figure Parameter Min Max Unit CLOCK TIMING CFREQ Clock Frequency 14.318 MHz Nominal 14.318 - 100 ppm 14.318 + 100 ppm MHz 24 MHz Nominal 24 -100 ppm 24+100 ppm MHz 48 MHz Nominal 48 -100 ppm 48+100 ppm MHz tCH Figure 91 Clock High Pulse Width 14.318 MHz Nominal 26 ns 24 MHz Nominal 16 ns 48 MHz Nominal 16 ns tCL Figure 91 Clock Low Pulse Width 14.318 MHz Nominal 8 ns 24 MHz Nominal 8 ns 48 MHz Nominal 8 ns CPU ACCESS TIMING tAR Figure 92 Address Valid to Read Active 15 ns tAW Figure 93 Address Valid to Write Active 15 ns tAES Figures 92, 93 AEN Signal Setup 15 ns tAEH Figures 92, 93 AEN Signal Hold 5 ns tDH Figure 93 Data Hold 2 ns tDS Figure 93 Data Setup 18 ns tHZ Figure 92 Data Bus Floating From Read Inactive 25 ns tRA Figure 92 Address Hold from Read Inactive 1 ns tRRV Figure 92 Read Cycle Recovery 45 ns tRD Figure 92 Read Strobe Width 60 1000 ns tRDH Figure 92 Read Data Hold 10 ns tRDV Figure 92 Data Valid From Read Active 55 ns tWA Figure 93 Address Hold from Write Inactive 1 ns tWRV Figure 93 Write Cycle Recovery 45 ns tWR Figure 93 Write Strobe Width 60 1000 ns tRI Figure 92 IRQn Reset Delay from Read Inactive 60 ns tWI Figure 93 IRQn Reset Delay from Write Inactive 60 ns RC Figure 92 Read Cycle Time (RC > tAR + tRD + tRRV) 123 ns WR Figure 93 Write Cycle Time (WR > tAW + tWR+ tWRV) 123 ns 2.4 0.4 2.0 0.8 Test Points 2.0 0.8 |
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