PC97338VLJ datasheet(130/221 Pages) NSC

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FIGURE 66. CTR Register Bitmap (EPP Mode)

The bits of this register have the identical function in

EPP modes as in SPP modes. See Section 4.2.5 for

a detailed description of each bit.

4.3.6

EPP Address Register, Offset 3

This port is added in EPP mode to enhance system

throughput by enabling registers in the remote device

to be directly addressed by hardware.

This port can be read or written. Writing to it initiates

an EPP device or register selection operation.

FIGURE 67. DTR Register Bitmap (EPP Mode)

4.3.7

EPP Data Port 0, Offset 4

This is a read/write port. Accessing it initiates device

read or write operations of bits 7-0.

FIGURE 68. DTR Register Bitmap (EPP Mode)

4.3.8

EPP Data Port 1, Offset 5

This is the second EPP data port. It is only accessed

to transfer bits 15 through 8 of a 16-bit read or write to

data port 0.

FIGURE 69. DTR Register Bitmap (EPP Mode)

4.3.9

EPP Data Port 2, Offset 6

This is the third EPP data port. It is only accessed to

transfer bits 16 to 23 of a 32-bit read or write to data

port 0.

FIGURE 70. EPP Data Port 2 Bitmap

321

Reset

Required

SPP or EPP Control

Offset 2

Printer Initialization Control (INIT)

Interrupt Enable

Direction Control

Reserved

Data Strobe Control

Automatic Line Feed Control

Parallel Port Input Control

321

Reset

Required

EPP Address

Offset 3

EPP Device or

321

Reset

Required

EPP Data

Port 0

Offset 4

EPP Device

Read or Write

Bits 7-0

321

Reset

Required

EPP Data

Port 1

Offset 5

D10

D12

D13

D14

D15

D11

EPP Device

Read or Write

Bits 15-8

321

Reset

Required

EPP Data

Port 2

Offset 6

D18

D20

D21

D22

D23

D16

D17

D19

EPP Device

Read or Write

Bits 23-16

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