PC97338VLJ datasheet(126/221 Pages) NSC

126 / 221 page

126

www.national.com

Bit 2 - IRQ Status

In all modes except Extended SPP, this bit is always

In Extended SPP mode (bit 7 of PTR is 1) this bit is

the IRQ status bit. It remains high unless the interrupt

request is enabled (bit 4 of CTR set high). This bit is

high except when latched low when the ACK signal

makes a low to high transition, indicating a character

is now being transferred to the printer.

Reading this bit resets it to 1.

0 - Interrupt requested in Extended SPP mode.

1 - No interrupt requested. (Default)

Bit 3 - ERR Status

This bit reflects the current state of the printer error

signal, ERR. The printer sets this bit low when

there is a printer error.

0 - Printer error.

1 - No printer error.

Bit 4 - SLCT Status

This bit reflects the current state of the printer se-

lect signal, SLCT. The printer sets this bit high

when it is online and selected.

0 - No printer selected.

1 - Printer selected and online.

Bit 5 - PE Status

This bit reflects the current state of the printer pa-

per end signal (PE). The printer sets this bit high

when it detects the end of the paper.

0 - Printer has paper.

1 - End of paper in printer.

Bit 6 - ACK Status

This bit reflects the current state of the printer ac-

knowledge signal, ACK. The printer pulses this

signal low after it has received a character and is

ready to receive another one. This bit follows the

state of the ACK pin.

0 - Character reception complete.

1 - No character received .

Bit 7 - Printer Status

This bit reflects the current state of the printer

BUSY signal. The printer sets this bit low when it

is busy and cannot accept another character.

This bit is the inverse of the (BUSY/WAIT) pin.

0 - Printer busy.

1 - Printer not busy.

4.2.5

Control Register (CTR), Offset 2

The control register provides all the output signals

that control the printer. Except for bit 5, it is a read and

write register.

Normally when the Control Register is read, the bit

values are provided by the internal output data latch.

These bit values can be superseded by the logic level

of the STB, AFD, INIT, and SLIN pins, if these pins

are forced high or low by an external voltage. To force

these signals high or low the corresponding bits

should be set to their inactive state (e.g., AFD, STB

and SLIN should all be 0, INIT should be 1).

Section 4.3.11 describes the transfer operations that

are possible in EPP mode.

FIGURE 62. CTR Register Bitmap (SPP Mode)

in PC87338

FIGURE 63. CTR Register Bitmap (SPP Mode)

Bit 0 - Data Strobe Control

Bit 0 directly controls the data strobe signal to the

printer via the STB pin.

This bit is the inverse of the STB pin.

765

210

Reset

Required

Control Register

(CTR)

Offset 2

Printer Initialization Control(INIT)

Interrupt Enable

Direction Control

Reserved

Data Strobe Control

Auto Line Feed Control

Parallel Port Input Control

765

210

Reset

Required

Control Register

(CTR)

Offset 2

Printer Initialization Control(INIT)

Interrupt Enable

Direction Control

Reserved

Data Strobe Control

Auto Line Feed Control

Parallel Port Input Control

PC97338VLJ bảng dữ liệu(PDF) 126 Page - National Semiconductor (TI)

PC97338VLJ bảng dữ liệu(HTML) 126 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL