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PC87360 bảng dữ liệu(PDF) 103 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện PC87360
Giải thích chi tiết về linh kiện  128-Pin LPC SuperI/O with Protection and Extensive GPIO Support
PDF  168 Pages
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nhà sản xuất  NSC [National Semiconductor (TI)]
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PC87360 bảng dữ liệu(HTML) 103 Page - National Semiconductor (TI)

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3.0 System Wake-Up Control (SWC) (Continued)
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3.4.30
Standby GPIO Pin Configuration Register (SBGPCFG)
This is a group of eight identical configuration registers, each of which is associated with one GPIOE/GPIE pin. The entire
set is mapped to the same address. The mapping scheme is based on the Standby GPIO Pin Select (SBGPSEL) register
that functions as an index register, and the specific Standby GPIO Pin Configuration register that reflects the configuration
of the currently selected pin.
Bits 0-3 are applicable only for pins GPIOE0-5. Bits 4-6 are applicable for all GPIOE/GPIE pins.
Location:
Bank 3, Offset 14h
Type:
R/W (bit 3 is set only)
For GPIOE and GPIE:
Bit
76543210
Name
Reserved
Event
Debounce
Enable
Event
Polarity
Event Type
Lock
Pull-Up
Control
Output
Type
Output
Enable
Reset
01000100
Bit
Description
7
Reserved
6
Event Debounce Enable
0: Disabled
1: Enabled (default)
5
Event Polarity. This bit defines the polarity of the signal that causes a detection of an event from the
corresponding GPIO pin.
0: Falling edge or low level input (default)
1: Rising edge or high level input
4
Event Type. This bit defines the signal type that causes a detection of an event from the corresponding GPIO
pin.
0: Edge input (default)
1: Level input
3
Lock. This bit locks bits 2-0 of this register. These bits are associated with the GPIO pin currently selected by
the SBGPSEL register. Once this bit is set to 1 by software, it can only be cleared to 0 by VSB power-up reset.
0: No effect (default at VSB power-up reset)
1: Direction, output type, pull-up and output value locked
2
Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.
It supports open-drain output signals with internal pull-ups and TTL input signals.
0: Disabled
1: Enabled (default)
1
Output Type. This bit controls the output buffer type (open-drain or totem pole) of the corresponding GPIO pin.
0: Open-drain (default)
1: Push-pull
0
Output Enable. For GPIOE and GPIE, this bit indicates the GPIO pin output state. It has no effect on input.
0: TRI-STATE (default for GPIOE/GPIE)
1: Output enabled



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