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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PC87360 bảng dữ liệu(PDF) 69 Page - National Semiconductor (TI) |
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PC87360 bảng dữ liệu(HTML) 69 Page - National Semiconductor (TI) |
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69 / 168 page  2.0 Device Architecture and Configuration (Continued) 69 www.national.com 2.16 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION 2.16.1 General Description This module includes two Fan Speed Control units and two Fan Speed Monitor units. The 10 runtime registers of the four functional blocks are arranged in the address space shown in Table 30. The base address is 16-byte aligned. Address bits 0-3 are used to indicate the register offset. Table 30. Runtime Registers in FSCM Address Space 2.16.2 Logical Device 9 (FSCM) Configuration Table 31 lists the configuration registers which affect the Fan Speed Controls and the Fan Speed Monitors. Only the last one (F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others. Table 31. FSCM Configuration Registers Offset Mnemonic Register Name Function 00h FCPSR0 Fan Control 0 Pre-Scale Fan Speed Control 0 01h FCDCR0 Fan Control 0 Duty Cycle 02h FCPSR1 Fan Control 1 Pre-Scale Fan Speed Control 1 03h FCDCR1 Fan Control 1 Duty Cycle 04h-05h Reserved 06h FMTHR0 Fan Monitor 0 Threshold Fan Speed Monitor 0 07h FMSPR0 Fan Monitor 0 Speed 08h FMCSR0 Fan Monitor 0 Control & Status 09h FMTHR1 Fan Monitor 1 Threshold Fan Speed Monitor 1 0Ah FMSPR1 Fan Monitor 1 Speed 0Bh FMCSR1 Fan Monitor 1 Control & Status 0Ch-0Fh Reserved Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register. R/W 00h 60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bit 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h F0h Fan Speed Control and Monitor Configuration 1 register R/W 00h |
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