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PC87360 bảng dữ liệu(PDF) 102 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện PC87360
Giải thích chi tiết về linh kiện  128-Pin LPC SuperI/O with Protection and Extensive GPIO Support
PDF  168 Pages
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nhà sản xuất  NSC [National Semiconductor (TI)]
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3.0 System Wake-Up Control (SWC) (Continued)
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Event Configuration
Each pin in the SBGPIO port is a potential input event source. The event detection can trigger a system notification upon predeter-
mined behavior of the source pin. The SBGPIO Pin Configuration register determines the event detection trigger type for the system
notification.
• Event Type and Polarity - Two trigger types of event detection are supported: edge and level. An edge event may be
detected upon a source pin transition either from high to low or low to high. A level event may be detected when the
source pin is in active level. The trigger type is determined by Event Type (bit 4). The direction of the transition (for edge)
or the polarity of the active level (for level) is determined by Event Polarity (bit 5).
• Event Debounce Enable - The input signal can be debounced for about 15 msec before entering the detector. The signal
state is transferred to the detector only after a debouncing period during which the signal has no transitions, to ensure
that the signal is stable. The debouncer adds 15 msec delay to both assertion and de-assertion of the event pending
indicator. Therefore, when working with a level event and system notification by either SMI or IRQ, it is recommended
to disable the debounce if the delay in the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event
Debounce Enable (bit 6 of the SBGPIO Pin Configuration register).
3.4.29
Standby GPIO Pin Select Register (SBGPSEL)
This register selects the GPIOE/GPIE pin (port number and pin number) to be configured (the register accessed by the
Standby GPIO Pin Configuration register). This register is reset to 00h on VPP power-up or software reset.
When port 0 is selected, bits 2-0 select between pins GPIE7,6 and GPIOE5-0.
Location:
Bank 3, Offset 13h
Type:
R/W
Bit
76543210
Name
Reserved
Port Select
Reserved
Pin Select
Reset
00000000
Bit
Description
7-5
Reserved
4
Port Select. This bit selects the GPIO port to be configured.
0: Port 0 (default)
1: Reserved
3
Reserved
2-0
Pin Select. These bits select the GPIO pin to be configured in the selected port.
000, 001, ... 111:The binary value of the pin number, 0, 1, ... 7 respectively (default=0)



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