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PC87303 bảng dữ liệu(PDF) 51 Page - National Semiconductor (TI) |
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PC87303 bảng dữ liệu(HTML) 51 Page - National Semiconductor (TI) |
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51 / 114 page  40 FDC Command Set Description (Continued) 42 COMMAND SET SUMMARY CONFIGURE Command Phase 0 0 0 1 0011 0 0 0 0 0000 0 EIS FIFO POLL THRESH PRETRK Execution Phase Internal registers written Result Phase None DUMPREG Command Phase 00001110 Execution Phase Internal registers read Result Phase PTR Drive 0 PTR Drive 1 PTR Drive 2 PTR Drive 3 Step Rate Time Motor Off Time Motor On Time DMA Sector per TrackEnd of Track (Note) LOCK 0 DC3 DC2 DC1 DC0 GAP WG 0 EIS FIFO POLL THRESH PRETRK Note Sectors per Track parameter returned if last command issued was Format End of Track parameter returned if last command issued was Read or Write FORMAT TRACK Command Phase 0 MFM 0 0 1 1 0 1 X X XXXHDDR1 DR0 Bytes per Sector Sectors per Track Format Gap Data Pattern Execution Phase System transfers four ID bytes (track head sector bytessector) per sector to the floppy control- ler via DMA or Non-DMA modes The entire track is format- ted The data block in the Data Field of each sector is filled with the data pattern byte Result Phase Status Register 0 Status Register 1 Status Register 2 Undefined Undefined Undefined Undefined INVALID Command Phase Invalid Op Codes Execution Phase None Result Phase Status Register 0 (80h) LOCK Command Phase LOCK0010100 Execution Phase Internal Lock register is written Result Phase 000LOCK0000 MODE Command Phase 00 0 0 0 0 0 1 TMR IAF IPS 0 LOW PWR 1 ETR FWR FRD BST R255 0 0 0 0 DENSEL BFR WLD Head Settle 00 0 0 0 RG 0 PU Execution Phase Internal registers are written Result Phase None NSC Command Phase 00011000 Execution Phase None Result Phase 01110011 PERPENDICULAR MODE Command Phase 0 0 0100 1 0 OW 0 DC3 DC2 DC1 DC0 GAP WG 51 |
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