STS1TX datasheet(46/70 Pages) STMICROELECTRONICS

tên linh kiện	STS1TX

Giải thích chi tiết về linh kiện	Industrial monitoring and control

PDF	70 Pages

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46 / 70 page

Transmission and reception

STS1TX

46/70

DocID025109 Rev 1

synchronization of an external data source, a data clock signal is also provided on one

of the GPIO pins. Data are sampled by the device on the rising edge of such clock

signal; it is the responsibility of the external data source to provide a stable input at this

edge.

•

3 - PN9 mode: a pseudo-random binary sequence is generated internally. This mode is

provided for test purposes only.

9.7

Data FIFO

In the STS1TX there is a TX FIFO for data to be transmitted, which is 96 bytes in length.

The SPI interface is used to write to the TX FIFO (see Figure 9) starting from the address

0xFF.

Figure 9. Threshold of the linear FIFO

The FIFO has two programmable thresholds: FIFO almost full and FIFO almost empty.

The FIFO almost full event occurs when the data crosses the threshold from below to

above. The TX FIFO almost empty threshold can be configured using the field TXAETHR in

the FIFO_CONFIG[0] register.

STS1TX bảng dữ liệu(PDF) 46 Page - STMicroelectronics