STMPE321QTR datasheet(10/40 Pages) STMICROELECTRONICS

10 / 40 page

I2C interface

STMPE321

10/40

Doc ID 15791 Rev 3

I2C interface

The following features are supported by the I2C interface:

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I2C slave device

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Compliance with Philips I2C specification version 2.1

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Standard (up to 100 kbps) and fast (up to 400 kbps) modes.

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7-bit and 10-bit device addressing modes

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General call

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Start/Restart/Stop

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I2C address is 0x58 (0xB0/0xB1 for write/read, including the LSB)

Start condition

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.

A Start condition must precede any data/command transfer. The device continuously

monitors for a Start condition and does not respond to any transaction unless one is

encountered.

Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.

A Stop condition terminates communication between the slave device and bus master. A

read command that is followed by NoAck can be followed by a Stop condition to force the

slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

next I2C transaction. A Stop condition at the end of a write command stops the write

operation to the registers.

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter

releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls

the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave

the SDATA in high state if it does not acknowledge the receipt of the data.

Data Input

The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA

signal must be stable during the rising edge of SCLK and the SDATA signal must change

only when SCLK is driven low.

Memory addressing

For the bus master to communicate to the slave device, the bus master must initiate a Start

condition, followed by the slave device address. Accompanying the slave device address,

there is a Read/WRITE bit (R/W). The bit is set to 1 for a read operation, and 0 for a write

operation.

If a match occurs on the slave device address, the corresponding device gives an

acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself

from the bus by not responding to the transaction.

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