NSC800 datasheet(9/76 Pages) NSC

9 / 76 page

60 Pin Descriptions (Continued)

Status (SO S1)

Bus status outputs provide encoded infor-

mation regarding the current M cycle as follows

Machine Cycle

Status

Control

IOM

Opcode Fetch

Memory Read

Memory Write

IO Read

IO Write

Halt

Internal Operation

Acknowledge of Int

ALE is not suppressed in this cycle

This is the cycle that occurs immediately after the CPU accepts an inter-

rupt (RSTA RSTB RSTC INTR NMI)

Note 1

During halt CPU continues to do dummy opcode fetch from location

following the halt instruction with a halt status This is so CPU can continue

to do its dynamic RAM refresh

Note 2

No early status is provided for interrupt or hardware restarts

63 INPUTOUTPUT SIGNALS

Multiplexed AddressData AD(0 – 7)

Active high

At RD Time

Input data to CPU

At WR Time

Output data from CPU

At Falling Edge Least significant byte of address

of ALE Time

during memory reference cycle 8-bit

port address during IO reference

cycle

During BREQ

High impedance

BACK Cycle

70 Connection Diagrams

Dual-In-Line Package

Top View

TLC5171 – 10

Order Number NSC800D or N

See NS Package D40C or N40A

Chip Carrier Package

Top View

TLC5171 – 11

Order Number NSC800E or V

See NS Package E44B or V44A

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