MPC8240EC datasheet(16/52 Pages) MOTOROLA

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MPC8240 Integrated Processor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

Figure 10 shows the input timing diagram for mode select signals.

Figure 10. Input Timing Diagram for Mode Select Signals

1.4.2.4

Output AC Timing Specification

Table 9 provides the processor bus AC timing specifications for the MPC8240. See Figure 8 and Figure 9

for the input-output timing diagrams referenced to SDRAM_SYNC_IN and PCI_SYNC_IN, respectively.

Figure 11 shows the AC test load for the MPC8240.

Table 9. Output AC Timing Specifications

At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V

Num

Characteristic 3, 6

Min

Max

Unit

Notes

12a

PCI_SYNC_IN to output valid, 66 MHz PCI, with MCP in the default

logic 1 state and CKE pulled down to logic 0 state (see Figure 10)

—

6.0

2, 4

PCI_SYNC_IN to output valid, 33 MHz PCI, with MCP and CKE in the

default logic 1 state (see Figure 10)

—

8.0

2, 4

12b1 SDRAM_SYNC_IN to output valid (for memory control address and

data signals accessing DRAM in flow-through mode)

—7.0

12b2 SDRAM_SYNC_IN to output valid (for memory control address and

data signals accessing DRAM in registered mode)

—6.0

12b3 SDRAM_SYNC_IN to output valid (for memory control address and

data signals accessing non-DRAM)

—7.0

12c

SDRAM_SYNC_IN to output valid (for all others)

—

7.0

12d

SDRAM_SYNC_IN to output valid (for I2C)

—

5.0

13a

Output hold, 66 MHz PCI, with MCP in the default logic 1 state and

CKE pulled down to logic 0 state (see Figure 10)

1.0

—

2, 4, 5

Output hold, 33 MHz PCI, with MCP and CKE in the default logic 1

state (see Figure 10)

2.0

—

2, 4, 5

13b

Output hold (all others)

—

14a

PCI_SYNC_IN to output high impedance (for PCI)

—

14.0

2, 4

VM = Midpoint Voltage (1.4 V)

11b

10e

HRST_CPU/HRST_CTRL

2.0 V

0.8 V

Mode Pins

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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