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MPC8240 Integrated Processor Hardware Specifications

Document Revision History

0.5

Removed references to GVDD = 2.5 V until characterization of the memory interface at this voltage has

been completed.

Corrected Figure 2 power supply ramp-up time to be before the 100 ms PLL relock time.

Table 3:

• Deleted input leakage specification @ LVDD = 5.5 V.

• Changed minimum ‘Input High Voltage for PCI only’ from 0.5*OVDodaoD to 0.65*OVDD and added

Note 6.

• Changed condition on ‘Input Low Voltage,’ VIL, from ‘All inputs except OSC_IN’ to ‘All inputs except

PCI_SYNC_IN.’

• Replaced minimum CVIH formula, 0.5*OVDD, with 2.4-V value.

• Replaced maximum CVIL formula, 0.3*OVDD, with 0.4-V value.

Added Note 10 to Table 5.

Changed minimum memory bus frequency of operation from 25 to 33 MHz in Table 6 to coincide with

information shown in PLL_CFG Table 18.

Updated clock specifications in Table 7.

Updated input AC timing specifications in Table 8.

Updated output AC timing specifications in Table 9.

Replaced TBDs in Table 14 for specs 3, 5, and 6.

Table 17 renamed TEST3 (pin AF20) to TRIG_IN and renamed TEST4 (pin AC18) to TRIG_OUT; moved

both pins from Test/Configuration Signals group to Miscellaneous Signals group.

Added external pull-up resistor to LVDD recommendation for INTA signal in Table 17 and Section 1.7.5.

Added Note 19 to Table 17 about AVDD and LAVDD being internally connected; revised Section 1.7.1,

on filtering these pins.

Replaced HID1 column TBDs in Table 18 and deleted Note 1 resulting in renumbering notes throughout

Table 18.

Added Section 1.7.7, about PCI reference voltage.

Added note in Section 1.9, indicating ‘L=Standard Spec.’ part is only available in 200 MHz version of the

device. Changed ‘XPC’ to ‘MPC’ for consistency with other references in the document.

Table 19. Document Revision History (continued)

Revision

Number

Substantive Change(s)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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