AT89C51CC03U-RDTIM datasheet(130/195 Pages) ATMEL

130 / 195 page

130

AT89C51CC03

4182I–CAN–06/05

Serial Port Interface

(SPI)

The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial

communication between the MCU and peripheral devices, including other MCUs.

Features

Features of the SPI Module include the following:

•

Full-duplex, three-wire synchronous transfers

•

Master or Slave operation

•

Six programmable Master clock rates in master mode

•

Serial clock with programmable polarity and phase

•

Master Mode fault error flag with MCU interrupt capability

Signal Description

Figure 57 shows a typical SPI bus configuration using one Master controller and many

Slave peripherals. The bus is made of three wires connecting all the devices.

Figure 57. SPI Master/Slaves Interconnection

The Master device selects the individual Slave devices by using four pins of a parallel

port to control the four SS pins of the Slave devices.

Master Output Slave Input

(MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device.

The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,

it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)

is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output

(MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device.

The MISO line is used to transfer data in series from the Slave to the Master. Therefore,

it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit

word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

SPI Serial Clock (SCK)

This signal is used to synchronize the data transmission both in and out of the devices

through their MOSI and MISO lines. It is driven by the Master for eight clock cycles

which allows to exchange one Byte on the serial lines.

Slave Select (SS)

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay

low for any message for a Slave. It is obvious that only one Master (SS high level) can

drive the network. The Master may select each Slave device by software through port

pins (Figure 58). To prevent bus conflicts on the MISO line, only one slave should be

selected at a time by the Master for a transmission.

Slave 1

MISO

MOSI

SCK

Slave 3

Slave 4

Slave 2

VDD

Master

AT89C51CC03U-RDTIM bảng dữ liệu(PDF) 130 Page - ATMEL Corporation

AT89C51CC03U-RDTIM bảng dữ liệu(HTML) 130 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL