TMS320VC5501 datasheet(128/193 Pages) TI

128 / 193 page

Functional Overview

128

December 2002 − Revised November 2004

SPRS206H

Reserved

RTOS

DLOG

BERR

R, 0

R/W, 0

I2C

TINT1

DMAC3

DMAC2

INT4

DMAC0

XINT0

INT1

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−52. IFR1, IER1, DBIFR1, and DBIER1 Registers Layout

3.16.2

Interrupt Timing

The external interrupts (NMI and INT) are synchronized to the CPU by way of a two-flip-flop synchronizer. The

interrupt inputs are sampled on falling edges of the CPU clock. A sequence on the interrupt pin of 1–0–0–0

on consecutive cycles is required for an interrupt to be detected. Therefore, the minimum low pulse duration

on the external interrupts on the 5501 is three CPU clock periods.

TIM0, TIM1, WDTOUT, and HPI.HAS can be configured to generate interrupts to the CPU. When they are used

for this function, these pins will generate the interrupt associated with that module, i.e., TIM0 will generate

TINT0, HPI.HAS will generate DSPINT, etc. Three SYSCLK1 clock cycles must be allowed to pass between

consecutive interrupts generated using the HPI.HAS signal; otherwise, the last interrupt will be ignored

(i.e., a sequence of 0−1−1−1−0 on consecutive cycles is required for consecutive interrupts). For more

information on configuring TIM0, TIM1, WDTOUT, and HPI.HAS as interrupt pins, please refer to the

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for the timer pins and to

the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for

the HPI pin.

3.16.3

Interrupt Acknowledge

The IACK pin is used to indicate the receipt of an interrupt and that the program counter is fetching the interrupt

vector location designated on the address bus. As the CPU fetches the first word or the software vector, it

generates the IACK signal, which clears the appropriate interrupt flag bit. The IACK signal will go low for a total

of one CPU clock pulse and then go high again. For maskable interrupts, note that the CPU will not jump to

an interrupt service routine if the appropriate interrupt enable bit is not set; consequently, the IACK pin will not

go low when the interrupt is generated.

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