FDC37C93XAPM datasheet(92/280 Pages) SMSC

92 / 280 page

EPP 1.7 OPERATION

When the EPP 1.7 mode is selected in the

configuration register, the standard and bi-

directional modes are also available. If no EPP

Read, Write or Address cycle is currently

executing, then the PDx bus is in the standard or

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the

SPP Control Port and direction is controlled by

PCD of the Control port.

In EPP mode, the system timing is closely

coupled to the EPP timing. For this reason, a

watchdog timer is required to prevent system

lockup.

The timer indicates if more than 10

µsec have elapsed from the start of the EPP

cycle (nIOR or nIOW asserted) to the end of the

cycle nIOR or nIOW deasserted). If a time-out

occurs, the current EPP cycle is aborted and the

time-out condition is indicated in Status bit 0.

Software Constraints

Before an EPP cycle is executed, the software

must ensure that the control register bits D0, D1

and D3 are set to zero. Also, bit D5 (PCD) is a

logic "0" for an EPP write or a logic "1" for and

EPP read.

EPP 1.7 Write

The timing for a write operation (address or

data) is shown in timing diagram EPP 1.7 Write

Data or Address cycle.

IOCHRDY is driven

active low when nWAIT is active low during the

EPP cycle. This can be used to extend the cycle

time.

The write cycle can complete when

nWAIT is inactive high.

Write Sequence of Operation

The host sets PDIR bit in the control

This asserts

nWRITE.

The host selects an EPP register, places

data on the SData bus and drives nIOW

active.

The chip places address or data on PData

bus.

Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus contains valid

information, and the WRITE signal is valid.

nWAIT

asserted,

IOCHRDY

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

When the host deasserts nIOW the chip

deasserts nDATASTB or nADDRSTRB and

latches the data from the SData bus for the

PData bus.

Chip may modify nWRITE, PDIR and

nPDATA in preparation of the next cycle.

EPP 1.7 Read

The timing for a read operation (data) is shown

in timing diagram EPP 1.7 Read Data cycle.

IOCHRDY is driven active low when nWAIT is

active low during the EPP cycle. This can be

used to extend the cycle time. The read cycle

can complete when nWAIT is inactive high.

Read Sequence of Operation

The host sets PDIR bit in the control

This deasserts

nWRITE and tri-states the PData bus.

The host selects an EPP register and drives

nIOR active.

Chip asserts nDATASTB or nADDRSTRB

indicating that PData bus is tri-stated, PDIR

is set and the nWRITE signal is valid.

nWAIT

asserted,

IOCHRDY

deasserted until the peripheral deasserts

nWAIT or a time-out occurs.

The Peripheral drives PData bus valid.

FDC37C93XAPM bảng dữ liệu(PDF) 92 Page - SMSC Corporation

FDC37C93XAPM bảng dữ liệu(HTML) 92 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL